In a conventional semiconductor integrated circuit device, a semiconductor substrate is divided into several element regions for the different elements by a selective oxide film or field oxide film by the LOCOS (local oxidation of silicon) method, and then the corresponding required elements are closely formed in each element region.
FIGS. 21-30 show a conventional manufacturing process for making complementary n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) on the same substrate using the LOCOS isolation method, used for example in making the peripheral circuit portion of a dynamic random access memory (DRAM). In FIG. 21, a thin SiO.sub.2 film 2 is formed on one principal plane of a p.sup.- -type silicon substrate 1, and a mask 3 of silicon nitride is selectively formed on it to specify the location for an n-type well region. Then impurities are ion-implanted into substrate 1 through an opening 5 in mask 3 by irradiating substrate 1 with a phosphorous ion beam 4, an n-type impurity of a conductivity type opposite to that of substrate 1, to form an n-type well 6 in substrate 1.
Next, as shown in FIG. 22, a thick SiO.sub.2 layer 7 is selectively grown by LOCOS on n-type well 6 by thermal oxidation in a steam atmosphere. As shown in FIG. 23, after nitride mask 3 is removed, a p-type well 9 is formed in self-aligned fashion adjacent to n-type well 6 by irradiating a boron ion beam 8, a p-type impurity of the same conductivity type as substrate 1, using SiO.sub.2 layer 7 as a mask (well 9 can also be formed by a solid-phase diffusion of impurities). The respective impurities of wells 6 and 9 are diffused by annealing at a high temperature of 1100-1200.degree. C., so that the intended depth and impurity concentration are attained.
Then SiO.sub.2 layers 2 and 7 of the surface are removed by etching as shown in FIG. 24. As a result, a step difference 10, for example of about 1000-1500 .ANG., is formed between the two wells 6 and 9.
As shown in FIG. 25, after the formation of a surface oxide film 11, an oxidation-resistant mask 12 of silicon nitride is formed in a prescribed pattern on wells 6 and 9 using the step difference 10 between wells 6 and 9 as a reference mark. Then, using mask 12, a field SiO.sub.2 layer 13 is selectively formed by LOCOS oxidation around the periphery of each well.
Next, a photoresist mask 14 is formed as shown in FIG. 26 in a prescribed pattern for forming a channel stopper, and a boron ion beam 15, a p-type impurity, is irradiated through SiO.sub.2 layer 13 at openings 16 in mask 14 to ion-implant a p.sup.+ -type region 17 as a channel stopper at the periphery of p-type well 9.
As shown in FIG. 27, photoresist mask 14 is then removed, and another photoresist mask 18 is applied. A phosphorous ion beam 19, an n-type impurity, is irradiated through the SiO.sub.2 layer 13 at openings 20 in mask 18 to ion-implant an n.sup.+ -type region as a channel stopper 21 at the periphery of n-type well 6.
After growing a gate oxide film 22 on the surface of each well 6 and 9, polysilicon gate electrodes 23 and 24, insulating SiO.sub.2 layers 25, and nitride side walls 26 are respectively formed as shown in FIG. 28. Then, a photoresist mask 27 is applied to cover n-type well 6, and a phosphorous ion beam 28, an n-type impurity, is irradiated, so that n.sup.+ -type impurity-implanted regions (source and drain regions) 29, 30 are formed in self-aligned fashion in p-type well 9.
Photoresist mask 27 is removed and another photoresist mask 31 is formed as shown in FIG. 29. Then a boron ion beam 32, a p-type impurity, is irradiated, to impurity-implant p.sup.+ -type regions (source and drain regions) 33, 34 in a self-aligned fashion in n-type well 6. Then mask 31 is removed.
Next, as shown in FIG. 30, an insulating layer 35 is deposited on the entire surface, into which contact holes 36 are respectively formed to each impurity-implanted source/drain region 29, 30, 33, and 34, and respective electrodes 37, 38, 39, and 40 (source or drain electrodes) are deposited in the contact holes. Thus, an n-channel MOSFET Tr.sub.1 is made on p-type well 9 and a p-channel MOSFET Tr.sub.2 on n-type well 6.
However, this conventional manufacturing process has the following problems (a)-(e).
(a) The number of processes required for preparing and constructing necessary elements (here MOSFET transistors Tr.sub.1 and Tr.sub.2) in wells 6 and 9 is increased, and the process is complicated.
(b) Oxide films 7 (FIG. 22) and 13 (FIG. 25) selectively grown by LOCOS have tips with an A-shaped bird's beak. Since the residual stress on the bird's beak results in current leakage, etc. and is apt to deteriorate the reliability and electrical characteristics of the semiconductor device, it is necessary to remove the residual stress by a high-temperature annealing treatment. However, since oxide film 13 is grown by LOCOS after wells 6 and 9 are formed by ion beam irradiation (see FIG. 25), in practice it is necessary to add a high-temperature annealing treatment after the LOCOS step, increasing the number of processes. Moreover, such an annealing treatment is earlier required after LOCOS growing of oxide film 7 (see FIG. 22), so the annealing treatment after the LOCOS oxidation must be carried out at least twice.
(c) Selectively growing oxide film 13 by LOCOS (FIGS. 24, 25) introduces a step 10 between wells 6 and 9. Because step 10 remains even after subsequent processing, this process is not suitable for fine patterning. For example, when simultaneously patterning the polysilicon gate electrodes 23 and 24 shown in FIG. 28, the exposure pattern for the photoresist can be focused on only one of the two wells, so the other well is defocused. The result is either gate terminal 23 or 24 is not patterned as designed.
(d) It is difficult to match the impurity concentration profile required for forming wells 6 and 9 to the impurity concentration profile required for the desired threshold voltages of transistors Tr.sub.1 and Tr.sub.2 provided in these wells. In other words, after the well-forming ion implantation of FIGS. 21 and 23, in practice implanted impurities move in from the surface of wells 6, 9 by thermal diffusion (well diffusion) so that the impurity concentrations at the well surface and interior end up changed.
(e) For this reason, to obtain a transistor which operates at a desired threshold voltage, it is necessary to separately form a diffusion mask for threshold voltage control on the well and to rediffuse necessary impurities. Moreover, to obtain transistors with different threshold voltages, a different diffusion mask is required for each. Therefore, the number of masks increases, and the manufacturing process becomes more complicated.
Therefore, an object of our invention is to provide a better method of manufacturing semiconductor devices which enables easy control of impurity concentrations and fine patterning, by making removal of residual stress due to LOCOS growing compatible with the formation of deep wells.